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thread cpu utilization
by Jilong Kuang - SISA 26 Nov '13

26 Nov '13

Hello, I'm wondering if there is a way to get thread CPU utilization info for Fiasco.OC kernel in Genode. Best regards, Jilong -- Jilong Kuang Ph.D. | Samsung Research America - Silicon Valley (SRA-SV) Senior Research Engineer, Computer Science Lab t: 408-544-2705 c: 951-318-2995 jilong.kuang@...60...<mailto:jilong.kuang@...60...> Please consider the environment before printing this email. This message is intended only for the named recipient(s) above and may contain confidential or privileged information or protected attorney work product. If you are not the intended recipient, any review, dissemination, distribution or copying is strictly prohibited. If you have received this message in error, please immediately notify the sender and delete this message and its attachments from your computer and dispose of all other copies or printouts. Thank you.

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base-hw ,,, What is CACHE_LINE_SIZE_LOG2?
by bob 19 Nov '13

19 Nov '13

Hi, Is CACHE_LINE_SIZE_LOG2 the line length in 32 bit words of the L2 Instruction or Data caches? That's the only cache line length I see in the board spec of the am335x in its TRM. I'm having a problem the initial start of the kernel, which appear to hang when the MMU is switched on in init_virt_kernel function. The tlb should set up correctly as I've defined the boards physical ram and MMIO regions in the Core_tbl class. The CACHE_LINE_SIZE_LOG2 parameter appears to be used as the stride length for walking the tlb. It is currently set at 2 only because that's the value used in the Panda and imx53 boards board_base.h. If that's not the problem, I'm at a loss as to what the issue could be since the CPU object is straight cortex-a8 from the arm_v7 architecture. Any pointers to how to diagnose the issue would be a great help. Thanks, Bob Stewart

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NOVA : Intel IO ports and Guest Unrestricted mode.
by avinash singh 13 Nov '13

13 Nov '13

Hello Guys, I am experimenting with NOVA Microkernel and trying to run some code in guest mode. I am attaching test program which usage NOVA syscall binding interface to create test program. Objective of this test program to run cpuid and outb instruction in guest mode on intel machine. Here, I am launching intel vcpu in real mode paging disable with all necessary register setup properly in vcpu startup portal handler. Once you download this code, run make and modify run.sh to point NOVA hypervisor. I want to discuss two problem. Problem -1: This test program runs (guest mode code) cpuid instruction but outb/inb instruction never runs in guest mode. I see that for outb instruction gives IO portal invoked again and again. First, I delegate IO ports from Kernel in root pd. My vcpu execution context is created in root pd. I believe that IO ports should be accessible from guest mode after delegating IO ports from kernel to guest. Secondly, same code for AMD runs if I set proper AMD vcpu registers in startup handler. Problem -2 As Intel process supports unrestricted guest mode; Advantage of that, I can run real mode instruction in vCPU context with paging disable without doing any instruction interpretations. I set Unrestricted guest mode control bit in VMCS control registers, though intel vCPU never runs guest in unrestricted mode. But When I experiments this with KVM it works. My question is, does NOVA kernel supports to run intel cpu in unrestricted guest mode? or is there any trick to do that so. Please help me if I am missing something. Any help regarding these two issues would be very helpful. Regards Avinash Singh

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Re: Writing Pin-muxing registers in an am3359.
by Bob Stewart 05 Nov '13

05 Nov '13

Christian, Thanks for your thoughtful reply. I've been looking at an extension to IO memory services in the kernel to access a restricted region, and adding parametric enabling of it is a good idea. My thinking was that setting the pin-mux registers should be done a driver separate from the gpio driver and that driver should read a config file to get the settings, then exit. All the use cases I'm dealing with require an initial set up then the applications execute using those settings without changing them. I'm currently using foc but I intend to go the base-hw route shortly. If time permits, I'll look into using the handle_slow_trap Thread method as learning exercise. Again, thanks for the reply. Bob Sent with AquaMail for Android http://www.aqua-mail.com

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Writing Pin-muxing registers in an am3359.
by Bob Stewart 05 Nov '13

05 Nov '13

On a TI am3359 processor (Beaglebone Black) I'm attempting to attempting to control the GPIO pin-muxing through the Control subsystem registers which start at 0x4e100000. I can read and write to the GPIO0 through GPIO3 registers correctly through MMIO after attaching the device memory, but when I try to write to any of the pin mux registers nothing is written and no errors are output. The code I've written to set up pin muxing resides in a gpio driver which is a modified version of an am 33xx gpio driver I pulled from the ksyslabs.org repository. With verbosity turned on, I see the that the pin mux registers are attached to local memory: /Genode::Io_mem_session_component::Dataspace_attr Genode::Io_mem_session_component::_prepare_io_mem(const char*, Genode::Range_allocator*): I/O mem [44e10000,44e11000)// //[init -> gpio_drv] GPIO_control base is 0x44e10000 local is 0x4000/ I write a value of 5 to the register offset 0x800 into the Control dataspace: /[init -> gpio_drv] mmio write 0x4800: 0x00000005// //[init -> gpio_drv] void Omap_driver::set_pin_controls(int, int, int): B=1, P=0, Mode=5, Input=0, Offset=0/ In jdb I see that the value at 0x4800 has not changed after apparently writing 5 to it. I believe I've set up the IO memory mapping correctly, the values read from the pin muxing registers look correct, and the GPIO subsystem appears to be set up correctly as I can turn on and off some LEDs. Is there something I need to do to enable writing to the memory region containing the Control registers? Thanks for any help. Bob Stewart

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Choosing a Kernel
by Neal H. Walfield 05 Nov '13

05 Nov '13

Hi, I'm looking to run Genode on an ARM Cortex A8. I'm primarily interested in the security properties of the resulting system. I'm explicitly not interested in running multiple OS personalities or doing virtualization. What I do want is as pure an object capability system as possible and as small an attack surface as possible. This seems to suggest Fiasco.OC or OKL4, but perhaps the bare hardware kernel is better. I think NOVA doesn't come into question, because it only runs on x86. I couldn't find much information about the bare hardware kernel. I'd appreciate any pointers. Thanks! :) Neal

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Question about system architecture, noux and interprocess communication
by J.M. Becker 01 Nov '13

01 Nov '13

First I wanted to say, I've been following Genode for about a year and I'm very excited about its progress. My question has to do with Noux and how communication is done between processes, and the eventual porting of D-Bus. I'm unsure about just how isolated each noux process is, from other noux processes, and how something like d-bus could share information between running processes. In addition does each process always execute in it's own noux? and if so how could something like a ps command get information about all running processes? I'm just trying to get a handle of things before jumping in and attempting to port additional components. Thank you, -J.

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Request for Booting document
by GANESH MALOTH 30 Oct '13

30 Oct '13

Hi all, I want to boot my system using Genode Operating System. Can somebody suggest me document or link on "How to boot my system using Genode OS"? Looking forward for someone's response..... Thanking you, Maloth Naresh

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Booting option
by GANESH MALOTH 30 Oct '13

30 Oct '13

I want to boot my system with genode-2010-11.iso file(To check live CD demonstration). I first did it in virtual box, i got booted. Now i want to check with realistic booting. I have burnt cd using this iso file, followed instructions in genode.org about system configuration check up and all, and then gave boot options : Boot with cd-dvd and saved but i am not able to boot. Can somebody suggest me some options for it? Maloth Naresh IITM

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PCI passthrough in vancouver
by Salscheider, Niels Ole 23 Oct '13

23 Oct '13

Hello, I am trying to implement PCI passthrough in vancouver when using NOVA. For PCI passthrough, I have to handle MessageHostOp::OP_ATTACH_MSI (amongst others). This requires modifications to the Irq_connection / Irq_session. My current plan is to pass the bdf value through to the Irq_proxy_component, where I can use it to get the pci config space. This is then passed to the assign_gsi syscall. Apart from that, I have added two functions to read back the msi address and data. However, my current implementation hangs when I try to get the first device from a Pci::Connection in Irq_proxy_component. Does it make sense to pass the bdf value to the Irq_proxy_component or would you suggest another way to design the Irq_connection interface? Regards, Ole Intel GmbH Dornacher Strasse 1 85622 Feldkirchen/Muenchen, Deutschland Sitz der Gesellschaft: Feldkirchen bei Muenchen Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk Registergericht: Muenchen HRB 47456 Ust.-IdNr./VAT Registration No.: DE129385895 Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052

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