Dear list,
GSoC has accepted a project to port seL4 to RISC-V (64 bit) architecture, which is used in the lowRISC System-on-a-Chip (SoC) Open Source project. Further, lowRISC supports another project to port rump kernels to minimal RISC-V cores which lowRISC plans to use as I/O co-processors, for example as TCP/IP offload engines [1].
There are tool chains and ports of Linux kernels to RISC-V / lowRISC to run them in simulators and emulators (qemu), on FPGA (Xilinx Zynq), and ASIC [2, 3].
Although my HW/SW co-design skills are a bit rusty, I am tempted to reverse that and try such a port. In order to get a better idea about complexity and effort required, I currently study the sources of base-hw for ARMv7, and its recent port to x86_64 in the staging branch.
Is anyone aware of such a porting effort, or has anyone else an interest to run Genode base-hw on RISC-V64, and might want to chime in eventually?
Thanks, Rolf
[1] http://www.lowrisc.org/blog/2015/05/summer-of-code-students-for-lowrisc/ [2] http://riscv.org/ [3] https://github.com/ucb-bar/rocket-chip
Hi Rolf,
On 05/22/2015 02:55 PM, Rolf Sommerhalder wrote:
Dear list,
GSoC has accepted a project to port seL4 to RISC-V (64 bit) architecture, which is used in the lowRISC System-on-a-Chip (SoC) Open Source project. Further, lowRISC supports another project to port rump kernels to minimal RISC-V cores which lowRISC plans to use as I/O co-processors, for example as TCP/IP offload engines [1].
There are tool chains and ports of Linux kernels to RISC-V / lowRISC to run them in simulators and emulators (qemu), on FPGA (Xilinx Zynq), and ASIC [2, 3].
Although my HW/SW co-design skills are a bit rusty, I am tempted to reverse that and try such a port. In order to get a better idea about complexity and effort required, I currently study the sources of base-hw for ARMv7, and its recent port to x86_64 in the staging branch.
Is anyone aware of such a porting effort, or has anyone else an interest to run Genode base-hw on RISC-V64, and might want to chime in eventually?
I just started on this one, actually right now. The first step would be to build the Genode tool chain for RISC-V. So, if that is ready I can let you know. The next steps would roughly be:
1. Update Genode's cxx library 2. Get base-hw compiling 3. Add UART support and implement the platform dependent kernel part 4. Extent the dynamic linker 5. (look into libc)
So, maybe there is something for you there.
We aware of the efforts you described above.
Cheers,
Sebastian
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Rolf Sommerhalder -
Sebastian Sumpf