Hi, Is CACHE_LINE_SIZE_LOG2 the line length in 32 bit words of the L2 Instruction or Data caches? That's the only cache line length I see in the board spec of the am335x in its TRM.
I'm having a problem the initial start of the kernel, which appear to hang when the MMU is switched on in init_virt_kernel function. The tlb should set up correctly as I've defined the boards physical ram and MMIO regions in the Core_tbl class. The CACHE_LINE_SIZE_LOG2 parameter appears to be used as the stride length for walking the tlb. It is currently set at 2 only because that's the value used in the Panda and imx53 boards board_base.h. If that's not the problem, I'm at a loss as to what the issue could be since the CPU object is straight cortex-a8 from the arm_v7 architecture. Any pointers to how to diagnose the issue would be a great help.
Thanks,
Bob Stewart
Hi Bob,
The only purpose of the parameter CACHE_LINE_SIZE_LOG2 is to enable us flushing the level 1 data cache of ARM in base-hw selectively. It controls the granularity of the flushing commands and is set correctly only for the Arndale board by now. The value "2" is the least possible value for ARM and slows flushing in the worst case while a value that would be higher than the correct value might cause data incoherence. Long story short: you can use "2" if you don't find the correct value in the level-1-cache description of your board spec.
Do you know which revision of Cortex-A8 (r1p1..r3p2) your board uses? Maybe there are quirks in your revision that base-hw doesn't support by now.
Have you checked whether the mappings you're adding to core TLB cover the text and BSS segment of the bin/core image?
You can also deactivate caches temporarily by initializing Arm::Cpu::Sctlr::C and Arm::Cpu::Sctlr::I in Arm::Cpu::Sctlr::common with 0 (base-hw/src/core/cpu/arm.h). This would at least limit the candidates.
PS: there is an open issue "base-hw crashes without caches" but as long as you're not above core/init this shouldn't affect you.
Cheers, Martin
On 15.11.2013 18:16, bob wrote:
Hi, Is CACHE_LINE_SIZE_LOG2 the line length in 32 bit words of the L2 Instruction or Data caches? That's the only cache line length I see in the board spec of the am335x in its TRM.
I'm having a problem the initial start of the kernel, which appear to hang when the MMU is switched on in init_virt_kernel function. The tlb should set up correctly as I've defined the boards physical ram and MMIO regions in the Core_tbl class. The CACHE_LINE_SIZE_LOG2 parameter appears to be used as the stride length for walking the tlb. It is currently set at 2 only because that's the value used in the Panda and imx53 boards board_base.h. If that's not the problem, I'm at a loss as to what the issue could be since the CPU object is straight cortex-a8 from the arm_v7 architecture. Any pointers to how to diagnose the issue would be a great help.
Thanks,
Bob Stewart
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On 11/15/2013 01:13 PM, Martin Stein wrote:
Hi Bob,
The only purpose of the parameter CACHE_LINE_SIZE_LOG2 is to enable us flushing the level 1 data cache of ARM in base-hw selectively. It controls the granularity of the flushing commands and is set correctly only for the Arndale board by now. The value "2" is the least possible value for ARM and slows flushing in the worst case while a value that would be higher than the correct value might cause data incoherence. Long story short: you can use "2" if you don't find the correct value in the level-1-cache description of your board spec.
Do you know which revision of Cortex-A8 (r1p1..r3p2) your board uses? Maybe there are quirks in your revision that base-hw doesn't support by now.
Have you checked whether the mappings you're adding to core TLB cover the text and BSS segment of the bin/core image?
You can also deactivate caches temporarily by initializing Arm::Cpu::Sctlr::C and Arm::Cpu::Sctlr::I in Arm::Cpu::Sctlr::common with 0 (base-hw/src/core/cpu/arm.h). This would at least limit the candidates.
PS: there is an open issue "base-hw crashes without caches" but as long as you're not above core/init this shouldn't affect you.
Cheers, Martin
On 15.11.2013 18:16, bob wrote:
Hi, Is CACHE_LINE_SIZE_LOG2 the line length in 32 bit words of the L2 Instruction or Data caches? That's the only cache line length I see in the board spec of the am335x in its TRM.
I'm having a problem the initial start of the kernel, which appear to hang when the MMU is switched on in init_virt_kernel function. The tlb should set up correctly as I've defined the boards physical ram and MMIO regions in the Core_tbl class. The CACHE_LINE_SIZE_LOG2 parameter appears to be used as the stride length for walking the tlb. It is currently set at 2 only because that's the value used in the Panda and imx53 boards board_base.h. If that's not the problem, I'm at a loss as to what the issue could be since the CPU object is straight cortex-a8 from the arm_v7 architecture. Any pointers to how to diagnose the issue would be a great help.
Thanks,
Bob Stewart
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Thanks Martin for the quick response.
The Technical Reference Manual for the Am335X doesn't reference a rev number for the Cortex A8 version, but I'll keep looking at a couple of other manuals. I'll go over all the System Control bit settings and compare them to the current Cortex-A8 manual to see if that tells me anything.
The core tlb I created defines a RAM region that cover the entire RAM available on the board, which covers the .text and .bss sections. Also includes two MMIO regions that cover controls for devices and the devices themselves.
Setting the C and the I bits the System Control register to zero had no effect.
I'll dig deeper into the CPU behavior and see what I can find.
Bob
On 11/15/2013 03:01 PM, bob wrote:
On 11/15/2013 01:13 PM, Martin Stein wrote:
Hi Bob,
The only purpose of the parameter CACHE_LINE_SIZE_LOG2 is to enable us flushing the level 1 data cache of ARM in base-hw selectively. It controls the granularity of the flushing commands and is set correctly only for the Arndale board by now. The value "2" is the least possible value for ARM and slows flushing in the worst case while a value that would be higher than the correct value might cause data incoherence. Long story short: you can use "2" if you don't find the correct value in the level-1-cache description of your board spec.
Do you know which revision of Cortex-A8 (r1p1..r3p2) your board uses? Maybe there are quirks in your revision that base-hw doesn't support by now.
Have you checked whether the mappings you're adding to core TLB cover the text and BSS segment of the bin/core image?
You can also deactivate caches temporarily by initializing Arm::Cpu::Sctlr::C and Arm::Cpu::Sctlr::I in Arm::Cpu::Sctlr::common with 0 (base-hw/src/core/cpu/arm.h). This would at least limit the candidates.
PS: there is an open issue "base-hw crashes without caches" but as long as you're not above core/init this shouldn't affect you.
Cheers, Martin
On 15.11.2013 18:16, bob wrote:
Hi, Is CACHE_LINE_SIZE_LOG2 the line length in 32 bit words of the L2 Instruction or Data caches? That's the only cache line length I see in the board spec of the am335x in its TRM.
I'm having a problem the initial start of the kernel, which appear to hang when the MMU is switched on in init_virt_kernel function. The tlb should set up correctly as I've defined the boards physical ram and MMIO regions in the Core_tbl class. The CACHE_LINE_SIZE_LOG2 parameter appears to be used as the stride length for walking the tlb. It is currently set at 2 only because that's the value used in the Panda and imx53 boards board_base.h. If that's not the problem, I'm at a loss as to what the issue could be since the CPU object is straight cortex-a8 from the arm_v7 architecture. Any pointers to how to diagnose the issue would be a great help.
Thanks,
Bob Stewart
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Thanks Martin for the quick response.
The Technical Reference Manual for the Am335X doesn't reference a rev number for the Cortex A8 version, but I'll keep looking at a couple of other manuals. I'll go over all the System Control bit settings and compare them to the current Cortex-A8 manual to see if that tells me anything.
The core tlb I created defines a RAM region that cover the entire RAM available on the board, which covers the .text and .bss sections. Also includes two MMIO regions that cover controls for devices and the devices themselves.
Setting the C and the I bits the System Control register to zero had no effect.
I'll dig deeper into the CPU behavior and see what I can find.
Bob
p.s. I did find out from the Beaglebone community that the Cortex-A8 version is r3p2.
Hi Bob,
The core tlb I created defines a RAM region that cover the entire RAM available on the board, which covers the .text and .bss sections. Also includes two MMIO regions that cover controls for devices and the devices themselves.
Setting the C and the I bits the System Control register to zero had no effect.
I'll dig deeper into the CPU behavior and see what I can find.
without looking specifically at Cortex-A8, I have two ideas of what could go wrong:
First, the only Cortex-A8-based platform supported by base-hw so far is i.MX53. In contrast to most low-cost ARM-platforms, i.MX53 starts the kernel in secure mode. Maybe your platform starts the kernel in non-secure mode? If I remember right, the secure/non-secure mode must be distinguished when setting up mappings in the page table.
Second, may it be that enabling the MMU actually succeeds but the UART device is not mapped correctly? As soon as the MMU gets activated, all I/O accesses go through the MMU as well. You could try out the following experiment:
1. Enable the MMU (via the existing call of 'init_virt_kernel' in kernel.cc) 2. Immediately disable the MMU again (add a call to 'init_phys_kernel' directly after the 'init_virt_kernel' call. 3. Print a message. 4. Enable the MMU again.
If you see the message, you know that at least the code for disabling the MMU was successfully executed while the MMU was active. This would indicate that not the MMU but the mapping of your UART is the problem.
Cheers Norman
On 18.11.2013 11:42, Norman Feske wrote:
Maybe your platform starts the kernel in non-secure mode? If I remember right, the secure/non-secure mode must be distinguished when setting up mappings in the page table.
On ARMv7 a complete base-hw page-table is either secure or non-secure. A page table sets its secure bit automatically according to the mode that is active while the page table gets constructed (see base-hw/src/core/tlb/arm_v7.h). The decision, whether secure or non-secure mode is active (Arm_v7::Cpu::secure_mode()) depends on Board_base::SECURITY_EXTENSION (in base/include/platform/$YOUR_BOARD/drivers/board_base.h). So it might be that this parameter is set inappropriate for your board. When adding mappings to page tables, secure-mode setting doesn't have to be considered.
Martin
On 11/18/2013 06:04 AM, Martin Stein wrote:
On 18.11.2013 11:42, Norman Feske wrote:
Maybe your platform starts the kernel in non-secure mode? If I remember right, the secure/non-secure mode must be distinguished when setting up mappings in the page table.
On ARMv7 a complete base-hw page-table is either secure or non-secure. A page table sets its secure bit automatically according to the mode that is active while the page table gets constructed (see base-hw/src/core/tlb/arm_v7.h). The decision, whether secure or non-secure mode is active (Arm_v7::Cpu::secure_mode()) depends on Board_base::SECURITY_EXTENSION (in base/include/platform/$YOUR_BOARD/drivers/board_base.h). So it might be that this parameter is set inappropriate for your board. When adding mappings to page tables, secure-mode setting doesn't have to be considered.
Martin
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Thanks for the responses Normal and Martin.
Trying the suggestion that the uart set-up may be the issue showed that that was not the issue.
However, setting the SECURITY_EXTENSION to 1 did produce an interesting result, in that the kernel crashed with an "undefined instruction" message. I traced this down to a call to the Security Control register, specifically to the assembly code for the read which is "asm volatile ("mrc p15, 0, %[v], c1, c1, 0" : [v]"=r"(v) ::);". This is used in the method to get the security mode setting in the cpu object.According to the Armv7-A Architecture Reference Manual, the assembly code appears to be correct. I'm not sure how to interpret that. Does it mean that the Security control is just not implemented?
Thanks,
Bob
On 18.11.2013 16:22, bob wrote:
However, setting the SECURITY_EXTENSION to 1 did produce an interesting result, in that the kernel crashed with an "undefined instruction" message. I traced this down to a call to the Security Control register, specifically to the assembly code for the read which is "asm volatile ("mrc p15, 0, %[v], c1, c1, 0" : [v]"=r"(v) ::);". This is used in the method to get the security mode setting in the cpu object.According to the Armv7-A Architecture Reference Manual, the assembly code appears to be correct. I'm not sure how to interpret that. Does it mean that the Security control is just not implemented?
This suggests that your board doesn't implement the ARM trustzone extension and thus not provide the co-processor #15 register c1.c1.0. Does the board spec say anything about trustzone or secure/non-secure mode?
Martin
I dont see anything about trustzone extension or secuitry mode.I suspect it does not, but I'll check with the community.
Thanks,
Bob
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On November 18, 2013 10:31:36 AM Martin Stein <martin.stein@...1...> wrote:
On 18.11.2013 16:22, bob wrote:
However, setting the SECURITY_EXTENSION to 1 did produce an interesting
result, in that the kernel crashed with an "undefined instruction" message. I traced this down to a call to the Security Control register, specifically to the assembly code for the read which is "asm volatile ("mrc p15, 0, %[v], c1, c1, 0" : [v]"=r"(v) ::);". This is used in the method to get the security mode setting in the cpu object.According to the Armv7-A Architecture Reference Manual, the assembly code appears to be correct. I'm not sure how to interpret that. Does it mean that the Security control is just not implemented? This suggests that your board doesn't implement the ARM trustzone extension and thus not provide the co-processor #15 register c1.c1.0. Does the board spec say anything about trustzone or secure/non-secure mode?
Martin
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Hello,
The AM335x TRM states in "26.1 Functional Description"
The device always starts up in secure mode. The ROM Code takes care of early initialization. The ROM code switches the device into public mode. Hence the Public ROM Code provides run-time services for cache maintenance.
Sounds to me like the operation mode on the PandaBoard, so, the kernel should operate as if TrustZone is not there except for cache handling SMCs.
Regards
Thanks, Christian.
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On November 18, 2013 11:35:32 AM Christian Helmuth <christian.helmuth@...1...> wrote:
Hello,
The AM335x TRM states in "26.1 Functional Description"
The device always starts up in secure mode. The ROM Code takes care of early initialization. The ROM code switches the device into public mode. Hence the Public ROM Code provides run-time services for cache maintenance.
Sounds to me like the operation mode on the PandaBoard, so, the kernel should operate as if TrustZone is not there except for cache handling SMCs.
Regards
Christian Helmuth Genode Labs
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On 11/18/2013 11:00 AM, Bob Stewart wrote:
I dont see anything about trustzone extension or secuitry mode.I suspect it does not, but I'll check with the community.
Thanks,
Bob
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On November 18, 2013 10:31:36 AM Martin Stein <martin.stein@...1...> wrote:
On 18.11.2013 16:22, bob wrote:
However, setting the SECURITY_EXTENSION to 1 did produce an interesting
result, in that the kernel crashed with an "undefined instruction" message. I traced this down to a call to the Security Control register, specifically to the assembly code for the read which is "asm volatile ("mrc p15, 0, %[v], c1, c1, 0" : [v]"=r"(v) ::);". This is used in the method to get the security mode setting in the cpu object.According to the Armv7-A Architecture Reference Manual, the assembly code appears to be correct. I'm not sure how to interpret that. Does it mean that the Security control is just not implemented? This suggests that your board doesn't implement the ARM trustzone extension and thus not provide the co-processor #15 register c1.c1.0. Does the board spec say anything about trustzone or secure/non-secure mode?
Martin
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I haven't heard back from the TI E2E group, but if the kernel was not in the Secure state it would not be able to read the Scr register because it has restricted access. Thanks to Christian reading what I should have read, the kernel is starting in user mode. Do I have to generate some kind of excpetion in order to change the mode to a privileged one? How would I go about getting into a correct mode? Thanks for all the time you guys have spent responding to me. Bob
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Hi Bob,
On 11/18/2013 11:20 PM, bob wrote:
I haven't heard back from the TI E2E group, but if the kernel was not in the Secure state it would not be able to read the Scr register because it has restricted access. Thanks to Christian reading what I should have read, the kernel is starting in user mode. Do I have to generate some kind of excpetion in order to change the mode to a privileged one? How would I go about getting into a correct mode? Thanks for all the time you guys have spent responding to me.
I'm afraid, you misunderstood Christian's mail. He just stated, that the kernel starts in non-secure mode. It is most likely in supervisor mode, and not in user mode ;-)
So I assume the whole TrustZone discussion leads to a dead end. Everything is correct if you just set SECURITY_EXTENSION back to zero. If set to one, the kernel assumes to run in secure mode on top of a TrustZone supported CPU, which obviously isn't the case regarding your board. In general, setting the SECURITY_EXTENSION to zero is the safe path even if your platform is starting in secure mode. This flag should be switched on only, if the base-hw kernel acts as a TrustZone hypervisor.
I strongly advise you to follow Norman's second proposal to first check whether you've a working UART. First, I would print something before the MMU is enabled, just to ensure you've the right physical addresses used to initialize the UART driver. If that works, follow Norman's approach to enable, and immediately disable the MMU again, and then print something. Just to see, whether the MMU, and the kernel's page-table are really the problem.
Regards Stefan
Thanks Stefan. I did try Norman's suggestion of turning of the MMU after turning it on, nothing printed on the console.
Thanks for your help I'll keep digging though the system control settings to see what I can find.
Bob
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On November 19, 2013 4:40:20 AM Stefan Kalkowski <stefan.kalkowski@...1...> wrote:
Hi Bob,
On 11/18/2013 11:20 PM, bob wrote:
I haven't heard back from the TI E2E group, but if the kernel was not in
the Secure state it would not be able to read the Scr register because it has restricted access. Thanks to Christian reading what I should have read, the kernel is starting in user mode. Do I have to generate some kind of excpetion in order to change the mode to a privileged one? How would I go about getting into a correct mode?
Thanks for all the time you guys have spent responding to me.
I'm afraid, you misunderstood Christian's mail. He just stated, that the kernel starts in non-secure mode. It is most likely in supervisor mode, and not in user mode ;-)
So I assume the whole TrustZone discussion leads to a dead end. Everything is correct if you just set SECURITY_EXTENSION back to zero. If set to one, the kernel assumes to run in secure mode on top of a TrustZone supported CPU, which obviously isn't the case regarding your board. In general, setting the SECURITY_EXTENSION to zero is the safe path even if your platform is starting in secure mode. This flag should be switched on only, if the base-hw kernel acts as a TrustZone hypervisor.
I strongly advise you to follow Norman's second proposal to first check whether you've a working UART. First, I would print something before the MMU is enabled, just to ensure you've the right physical addresses used to initialize the UART driver. If that works, follow Norman's approach to enable, and immediately disable the MMU again, and then print something. Just to see, whether the MMU, and the kernel's page-table are really the problem.
Regards Stefan
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Sorry all, it is the uart settings! Apologise for wasting your time.
Thanks, Bob
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On November 19, 2013 7:23:47 AM Bob Stewart <robjsstewart@...196...> wrote:
Thanks Stefan. I did try Norman's suggestion of turning of the MMU after turning it on, nothing printed on the console.
Thanks for your help I'll keep digging though the system control settings to see what I can find.
Bob
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On November 19, 2013 4:40:20 AM Stefan Kalkowski <stefan.kalkowski@...1...> wrote:
Hi Bob,
On 11/18/2013 11:20 PM, bob wrote:
I haven't heard back from the TI E2E group, but if the kernel was not
in the Secure state it would not be able to read the Scr register because it has restricted access. Thanks to Christian reading what I should have read, the kernel is starting in user mode. Do I have to generate some kind of excpetion in order to change the mode to a privileged one? How would I go about getting into a correct mode?
Thanks for all the time you guys have spent responding to me.
I'm afraid, you misunderstood Christian's mail. He just stated, that the kernel starts in non-secure mode. It is most likely in supervisor mode, and not in user mode ;-)
So I assume the whole TrustZone discussion leads to a dead end. Everything is correct if you just set SECURITY_EXTENSION back to zero. If set to one, the kernel assumes to run in secure mode on top of a TrustZone supported CPU, which obviously isn't the case regarding your board. In general, setting the SECURITY_EXTENSION to zero is the safe path even if your platform is starting in secure mode. This flag should be switched on only, if the base-hw kernel acts as a TrustZone hypervisor.
I strongly advise you to follow Norman's second proposal to first check whether you've a working UART. First, I would print something before the MMU is enabled, just to ensure you've the right physical addresses used to initialize the UART driver. If that works, follow Norman's approach to enable, and immediately disable the MMU again, and then print something. Just to see, whether the MMU, and the kernel's page-table are really the problem.
Regards Stefan
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