Hi, Is CACHE_LINE_SIZE_LOG2 the line length in 32 bit words of the L2 Instruction or Data caches? That's the only cache line length I see in the board spec of the am335x in its TRM.
I'm having a problem the initial start of the kernel, which appear to hang when the MMU is switched on in init_virt_kernel function. The tlb should set up correctly as I've defined the boards physical ram and MMIO regions in the Core_tbl class. The CACHE_LINE_SIZE_LOG2 parameter appears to be used as the stride length for walking the tlb. It is currently set at 2 only because that's the value used in the Panda and imx53 boards board_base.h. If that's not the problem, I'm at a loss as to what the issue could be since the CPU object is straight cortex-a8 from the arm_v7 architecture. Any pointers to how to diagnose the issue would be a great help.
Thanks,
Bob Stewart