I'm about to start to bring up a base-hw implementation on an Arm Cortex A-7 quad core Allwinner H3 board. Has this already been done by anyone?
The A7 is "similar" to the A9 with the addition of LPAE. As opposed to the A9, it has GIC v2 and an SCU with an L2 Cache tightly coupled to it, mean that you can turn on or off the cache and that's all the control you have.
It looks like the Cortex A15 implementation already in base-hw would be a good model to follow to get the A7 running.
Bob Stewart
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