Hi Kranthi Tej,
Am 16.04.2017 um 16:15 schrieb Kranthi Tej:
Following up on the previous email, I've stumbled upon something while debugging. I've debugged the enable_mmu_and_caches function line by line. I've discovered that the lines which involved the address worked fine. It stops at:
Sctlr::enable_mmu_and_caches();
(repos/base-hw/src/core/include/spec/arm/cpu_support.h:509)
I've debugged (placed log messages after every line) the function further and observed that the problem is with
Sctlr::write(v) function
(repos/base-hw/src/core/include/spec/arm/cpu_support.h:111)
I've looked into the write function. But, I haven't been able to pinpoint what was going wrong. Could it be a problem with the function? Or, could it be a problem with the value being passed to it? (I haven't been completely able to tell that the problem isn't with the address. It could still be a problem.) I've also tried using the images built by Genode - 15.02 and 16.05. It stops with a "Pagefault in core thread" message after "kernel initialized".
Most likely it's not a problem with the write function but with the hardware implications of this specific write. This is the point where memory-management unit and caches are switched on for the first time implicitely moving execution from the physical to a virtual address space. As the Kernel has no pager, this means that the page table behind the virtual address space must already contain all stuff that is essential to the Kernel (and the Core main/pager functionality).
Could you please give me any pointers to go forward? I'm stuck here. Your help will be greatly appreciated.
I would lookup the pagefault IP denoted in the pagefault message first using 'genode-arm-objdump -DCl <BUILD_DIR>/var/run/<RUN_NAME>.core'. This should give you a hint what is missing in your page table. The MMIO regions to be included in the early page table are defined in [1].
It might help if you post the whole serial output of your test.
Cheers, Martin
[1] base-hw/src/bootstrap/spec/imx6/platform.cc