users November 2013

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15 participants
15 discussions

NOVA : Intel IO ports and Guest Unrestricted mode.
by avinash singh 13 Nov '13

13 Nov '13

Hello Guys, I am experimenting with NOVA Microkernel and trying to run some code in guest mode. I am attaching test program which usage NOVA syscall binding interface to create test program. Objective of this test program to run cpuid and outb instruction in guest mode on intel machine. Here, I am launching intel vcpu in real mode paging disable with all necessary register setup properly in vcpu startup portal handler. Once you download this code, run make and modify run.sh to point NOVA hypervisor. I want to discuss two problem. Problem -1: This test program runs (guest mode code) cpuid instruction but outb/inb instruction never runs in guest mode. I see that for outb instruction gives IO portal invoked again and again. First, I delegate IO ports from Kernel in root pd. My vcpu execution context is created in root pd. I believe that IO ports should be accessible from guest mode after delegating IO ports from kernel to guest. Secondly, same code for AMD runs if I set proper AMD vcpu registers in startup handler. Problem -2 As Intel process supports unrestricted guest mode; Advantage of that, I can run real mode instruction in vCPU context with paging disable without doing any instruction interpretations. I set Unrestricted guest mode control bit in VMCS control registers, though intel vCPU never runs guest in unrestricted mode. But When I experiments this with KVM it works. My question is, does NOVA kernel supports to run intel cpu in unrestricted guest mode? or is there any trick to do that so. Please help me if I am missing something. Any help regarding these two issues would be very helpful. Regards Avinash Singh

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Re: Writing Pin-muxing registers in an am3359.
by Bob Stewart 05 Nov '13

05 Nov '13

Christian, Thanks for your thoughtful reply. I've been looking at an extension to IO memory services in the kernel to access a restricted region, and adding parametric enabling of it is a good idea. My thinking was that setting the pin-mux registers should be done a driver separate from the gpio driver and that driver should read a config file to get the settings, then exit. All the use cases I'm dealing with require an initial set up then the applications execute using those settings without changing them. I'm currently using foc but I intend to go the base-hw route shortly. If time permits, I'll look into using the handle_slow_trap Thread method as learning exercise. Again, thanks for the reply. Bob Sent with AquaMail for Android http://www.aqua-mail.com

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Writing Pin-muxing registers in an am3359.
by Bob Stewart 05 Nov '13

05 Nov '13

On a TI am3359 processor (Beaglebone Black) I'm attempting to attempting to control the GPIO pin-muxing through the Control subsystem registers which start at 0x4e100000. I can read and write to the GPIO0 through GPIO3 registers correctly through MMIO after attaching the device memory, but when I try to write to any of the pin mux registers nothing is written and no errors are output. The code I've written to set up pin muxing resides in a gpio driver which is a modified version of an am 33xx gpio driver I pulled from the ksyslabs.org repository. With verbosity turned on, I see the that the pin mux registers are attached to local memory: /Genode::Io_mem_session_component::Dataspace_attr Genode::Io_mem_session_component::_prepare_io_mem(const char*, Genode::Range_allocator*): I/O mem [44e10000,44e11000)// //[init -> gpio_drv] GPIO_control base is 0x44e10000 local is 0x4000/ I write a value of 5 to the register offset 0x800 into the Control dataspace: /[init -> gpio_drv] mmio write 0x4800: 0x00000005// //[init -> gpio_drv] void Omap_driver::set_pin_controls(int, int, int): B=1, P=0, Mode=5, Input=0, Offset=0/ In jdb I see that the value at 0x4800 has not changed after apparently writing 5 to it. I believe I've set up the IO memory mapping correctly, the values read from the pin muxing registers look correct, and the GPIO subsystem appears to be set up correctly as I can turn on and off some LEDs. Is there something I need to do to enable writing to the memory region containing the Control registers? Thanks for any help. Bob Stewart

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Choosing a Kernel
by Neal H. Walfield 05 Nov '13

05 Nov '13

Hi, I'm looking to run Genode on an ARM Cortex A8. I'm primarily interested in the security properties of the resulting system. I'm explicitly not interested in running multiple OS personalities or doing virtualization. What I do want is as pure an object capability system as possible and as small an attack surface as possible. This seems to suggest Fiasco.OC or OKL4, but perhaps the bare hardware kernel is better. I think NOVA doesn't come into question, because it only runs on x86. I couldn't find much information about the bare hardware kernel. I'd appreciate any pointers. Thanks! :) Neal

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Question about system architecture, noux and interprocess communication
by J.M. Becker 01 Nov '13

01 Nov '13

First I wanted to say, I've been following Genode for about a year and I'm very excited about its progress. My question has to do with Noux and how communication is done between processes, and the eventual porting of D-Bus. I'm unsure about just how isolated each noux process is, from other noux processes, and how something like d-bus could share information between running processes. In addition does each process always execute in it's own noux? and if so how could something like a ps command get information about all running processes? I'm just trying to get a handle of things before jumping in and attempting to port additional components. Thank you, -J.

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users November 2013