base-hw ,,, What is CACHE_LINE_SIZE_LOG2?

[bob]

On 11/18/2013 06:04 AM, Martin Stein wrote:
> On 18.11.2013 11:42, Norman Feske wrote:
>> Maybe your platform starts the kernel in
>> non-secure mode? If I remember right, the secure/non-secure mode must be
>> distinguished when setting up mappings in the page table.
> On ARMv7 a complete base-hw page-table is either secure or non-secure. A
> page table sets its secure bit automatically according to the mode that
> is active while the page table gets constructed (see
> base-hw/src/core/tlb/arm_v7.h). The decision, whether secure or
> non-secure mode is active (Arm_v7::Cpu::secure_mode()) depends on
> Board_base::SECURITY_EXTENSION (in
> base/include/platform/$YOUR_BOARD/drivers/board_base.h). So it might be
> that this parameter is set inappropriate for your board. When adding
> mappings to page tables, secure-mode setting doesn't have to be considered.
>
> Martin
>
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Thanks for the responses Normal and Martin.

Trying the suggestion that the uart set-up may be the issue showed that 
that was not the issue.

However, setting the SECURITY_EXTENSION to 1 did produce an interesting 
result, in that the kernel crashed with an "undefined instruction" 
message. I traced this down to a call to the Security Control register, 
specifically to the assembly code for the read which is "asm volatile 
("mrc p15, 0, %[v], c1, c1, 0" : [v]"=r"(v) ::);". This is used in the 
method to get the security mode setting in the cpu object.According to 
the Armv7-A Architecture Reference Manual, the assembly code appears to 
be correct. I'm not sure how to interpret that. Does it mean that the 
Security control is just not implemented?

     Thanks,

         Bob