jitterentropy base genode nstime.h for virt riscv

Martin Stein martin.stein at genode-labs.com
Mon Feb 27 14:40:46 CET 2023

I'm sorry, I didn't get the second part of your mail.

On 27.02.23 13:55, Pranab Kumar Rout cs21m045 wrote:
> I tried to build it by looking at the header files corresponding to
> other architectures. I am not aware of opcode for riscv. Please guide me
> to write the correct code. what should be written in this header file
> for riscv.

The mechanics of the ARMv7 MRC can be found in the RM [1] by looking up
"mrc p15, 0, <Rt>, c9, c13, 0". If I'd be in your situation I'd look for
a similar semantic in the RISC-V manuals. The current RISC-V ISA used in
Genode is referenced in [2].

[1] https://developer.arm.com/documentation/ddi0406/latest/
[2] https://genodians.org/ssumpf/2021-02-24-riscv

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