Roadmap 2022

[Johannes Schlatow]

A happy new year to all of you!

> What's your reflection of Genode's past year?

Personally, I really enjoyed resuming the work with Genode and
switching to Sculpt as a daily driver. After a couple years of deep
sleep on my side, I started highly motivated into this endeavour.
Converting to Sculpt with a new Laptop was a little painful at times,
yet also gave me the opportunity to dig into a variety of topics and
familiarise myself with quite a bit of the current code base.
Figuratively speaking, it was a fun experience surfing the learning
curve most of the time. Though, enabling all peripherals (e.g. modem,
webcam, wifi) that I was used to on Sculpt took quite a bit longer than
I had expected. There are still a few uncompleted low-priority jobs
left.

My personal highlights have been that I got the opportunity to
continue two lines of work that I was already focused on when I first
got in touch with Genode. First, I revived the Zynq-7000 support in
Genode and started enabling the use of its FPGA. Secondly, I started
exploiting Genode's tracing capabilities to record and analyse
component interactions and component state. While test driving
the prototypical implementation for narrowing down some network
performance anomalies, I already enjoyed the ease with which one can
acquire trace data from a running Sculpt system.

> What are the topics you deem as most interesting to work on?

Making good use of the Zynq's FPGA in Genode and continuing on the
tracing capabilities are my top priorities (more details down below).
I'd also love to see my mailserver running on Genode at some point in
the future. A first step into this direction is to look into how
container images could be hosted on Genode. I doubt that I'll be able
to spend much time on this but would love to touch this topic if
time permits.

> Do you already have tangible plans you can share with us?

Regarding the FPGA topic, I am going to familiarise myself with the
Xilinx tools in order to build custom bitstreams. In particular, I'd
like to investigate solutions for guarding DMA via custom FPGA logic.
The main idea is to emulate the register interface of DMA-capable
devices in the FPGA and having a SystemMMU-like access control mechanism
controlled by the platform driver. As a side effect of working with
Zynq-based boards, I'll incrementally implement/port additional device
drivers (SD card, pin, some standard IP cores, ...).

When it comes to tracing, I am going to write a trace recorder
component with which one can extract different trace outputs from
multiple Genode components at the same time. Major output formats are
pcap files (capturing network traffic to be analysed with wireshark),
ctf traces (capturing component interactions and arbitrary checkpoints
to be visualised and analysed with TraceCompass), and log output. I
think this is realistically finished by the end of May so that it can
be put into good use for the rest of the year.

Another idea that I'd like to pursue is to leverage the tracing
capabilities for systematically identifying performance bottlenecks.
Having a tool for Genode similar to the coz profiler [1] could turn out
to be very helpful in narrowing down where performance optimisation has
the biggest impact.

[1] https://github.com/plasma-umass/coz

> Are there road blocks that stand in the way of your plans?
> 
> What is your vision of using Genode at the end of 2022?
> 

By the end of the year, I envision having sophisticated and easy-to-use
tracing tools for Genode that we are able to routinely use for
debugging and performance analysis.

On the FPGA topic, custom programmable logic will integrate nicely
into Genode and there will be corresponding documentation for how to
augment a resource-limited embedded Genode system with custom hardware
accelerators.

Best,
Johannes