[genode] base-hw: SMP support on I.MX6
Le Guan
guanle.ustc at ...9...
Fri Oct 2 19:42:32 CEST 2015
Hi Stefan,
I copied some macro definitions from freescale SDK, and I have validated
that it can kick off the remaining 3 cores. Below is the patched
repos/base-hw/src/core/include/spec/imx6/board.h. (Also attached).
/*
* \brief Board driver
* \author Stefan Kalkowski
* \author Martin Stein
* \date 2014-02-25
*/
/*
* Copyright (C) 2014-2015 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
#include <spec/imx/board_support.h>
#include <spec/cortex_a9/board_support.h>
#define REGS_SRC_BASE (0x020d8000) //!< Base address for SRC.
#define HW_SRC_SCR_ADDR (REGS_SRC_BASE + 0x0)
#define HW_SRC_GPR3_ADDR (REGS_SRC_BASE + 0x28)
#define HW_SRC_GPR5_ADDR (REGS_SRC_BASE + 0x30)
#define HW_SRC_GPR7_ADDR (REGS_SRC_BASE + 0x38)
#define HW_SRC_SCR (*(volatile hw_src_scr_t *) HW_SRC_SCR_ADDR)
#define HW_SRC_GPR3 (*(volatile hw_src_gpr3_t *) HW_SRC_GPR3_ADDR)
#define HW_SRC_GPR5 (*(volatile hw_src_gpr5_t *) HW_SRC_GPR5_ADDR)
#define HW_SRC_GPR7 (*(volatile hw_src_gpr7_t *) HW_SRC_GPR7_ADDR)
typedef unsigned int reg32_t;
typedef union _hw_src_gpr3
{
reg32_t U;
struct _hw_src_gpr3_bitfields
{
unsigned RESERVED0 : 32; //!< [31:0] Read/write bits, for general
purpose
} B;
} hw_src_gpr3_t;
typedef union _hw_src_gpr7
{
reg32_t U;
struct _hw_src_gpr7_bitfields
{
unsigned RESERVED0 : 32; //!< [31:0] Read/write bits, for general
purpose
} B;
} hw_src_gpr7_t;
typedef union _hw_src_gpr5
{
reg32_t U;
struct _hw_src_gpr5_bitfields
{
unsigned RESERVED0 : 32; //!< [31:0] Read/write bits, for general
purpose
} B;
} hw_src_gpr5_t;
typedef union _hw_src_scr
{
reg32_t U;
struct _hw_src_scr_bitfields
{
unsigned WARM_RESET_ENABLE : 1; //!< [0] WARM reset enable bit.
unsigned SW_GPU_RST : 1; //!< [1] Software reset for gpu
unsigned SW_VPU_RST : 1; //!< [2] Software reset for vpu
unsigned SW_IPU1_RST : 1; //!< [3] Software reset for ipu1
unsigned SW_OPEN_VG_RST : 1; //!< [4] Software reset for open_vg
unsigned WARM_RST_BYPASS_COUNT : 2; //!< [6:5] Defines the ckil
cycles to count before bypassing the MMDC acknowledge for WARM reset.
unsigned MASK_WDOG_RST : 4; //!< [10:7] Mask wdog_rst_b source.
unsigned EIM_RST : 1; //!< [11] EIM reset is needed in order to
reconfigure the eim chip select.
unsigned SW_IPU2_RST : 1; //!< [12] Software reset for ipu2
unsigned CORE0_RST : 1; //!< [13] Software reset for core0 only.
unsigned CORE1_RST : 1; //!< [14] Software reset for core1 only.
unsigned CORE2_RST : 1; //!< [15] Software reset for core2 only.
unsigned CORE3_RST : 1; //!< [16] Software reset for core3 only.
unsigned CORE0_DBG_RST : 1; //!< [17] Software reset for core0
debug only.
unsigned CORE1_DBG_RST : 1; //!< [18] Software reset for core1
debug only.
unsigned CORE2_DBG_RST : 1; //!< [19] Software reset for core2
debug only.
unsigned CORE3_DBG_RST : 1; //!< [20] Software reset for core3
debug only.
unsigned CORES_DBG_RST : 1; //!< [21] Software reset for debug of
arm platform only.
unsigned CORE1_ENABLE : 1; //!< [22] CPU core1 enable.
unsigned CORE2_ENABLE : 1; //!< [23] CPU core2 enable.
unsigned CORE3_ENABLE : 1; //!< [24] CPU core3 enable.
unsigned DBG_RST_MSK_PG : 1; //!< [25] Do not assert debug resets
after power gating event of cpu
unsigned RESERVED0 : 6; //!< [31:26] Reserved
} B;
} hw_src_scr_t;
#define HW_SRC_GPR3_WR(v) (HW_SRC_GPR3.U = (v))
#define HW_SRC_GPR5_WR(v) (HW_SRC_GPR5.U = (v))
#define HW_SRC_GPR7_WR(v) (HW_SRC_GPR7.U = (v))
namespace Genode
{
/**
* Board driver
*/
class Board : public Imx::Board, public Cortex_a9::Board {
public:
static void secondary_cpus_ip(void * const ip) {
HW_SRC_GPR3_WR((uint32_t) ip);
HW_SRC_SCR.B.CORE1_ENABLE = 1;
HW_SRC_GPR5_WR((uint32_t) ip);
HW_SRC_SCR.B.CORE2_ENABLE = 1;
HW_SRC_GPR7_WR((uint32_t) ip);
HW_SRC_SCR.B.CORE3_ENABLE = 1;
return;
}
static bool is_smp(){
return true;
}
};
}
#endif /* _BOARD_H_ */
Thanks for your amazing work.
Best regards,
Le Guan
On Fri, Oct 2, 2015 at 8:34 AM, Stefan Kalkowski <
stefan.kalkowski at ...1...> wrote:
> Hi Le Guan,
>
> can you provide the changes you did, so we are able to reproduce it?
>
> I know there are still issues with SMP on Cortex A9 in our current
> implementation. They are targeted by the work of Martin Stein on issue
> #1312 in our issue tracker:
>
> https://github.com/genodelabs/genode/issues/1312
>
> However, the provided solution only uses the Pandaboard, and is not yet
> ready for our master branch. But given your knowledge regarding the
> scratch register used to provide the entrypoints to the additional cpu
> cores, we could test it with the Wandboard.
>
> Regards
> Stefan
>
> On 09/30/2015 12:07 AM, Le Guan wrote:
> > Hello everyone,
> > I wonder if the current release supports SMP in base-hw. I read from the
> > genode book that base-hw has well supported SMP long time ago. But the
> > default configure in wandBoard sets NR_OF_CPUS to 1. When I change that
> > value to 4 and implement several auxiliary SMP functions and run the
> > program, there seems to be some error happen. Below is the output:
> >
> > core 0 enabled
> > kernel initialized
> > core 1 enabled
> > core 2 enabled
> > core 3 enabled
> > Genode 15.08-25-g5cf8c49 <local changes>
> > int main(): --- create local services ---
> > int main(): --- start init ---
> >
> >
> > The booting is stuck here. I have implemented the corresponding
> > Cpu::start_secondary_cpus, Cpu::primary_id() and Cpu::executing_id().
> What
> > else should I implement to boot SMP?
> >
> > Thanks in advance!
> > Best regards,
> > Le Guan
> >
> >
> >
> >
> ------------------------------------------------------------------------------
> >
> >
> >
> > _______________________________________________
> > genode-main mailing list
> > genode-main at lists.sourceforge.net
> > https://lists.sourceforge.net/lists/listinfo/genode-main
> >
>
> --
> Stefan Kalkowski
> Genode Labs
>
> http://www.genode-labs.com/ ยท http://genode.org/
>
>
> ------------------------------------------------------------------------------
> _______________________________________________
> genode-main mailing list
> genode-main at lists.sourceforge.net
> https://lists.sourceforge.net/lists/listinfo/genode-main
>
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