Port of base-hw to RISC-V / lowRISC ?
rolf.sommerhalder at ...278...
Fri May 22 14:55:38 CEST 2015
GSoC has accepted a project to port seL4 to RISC-V (64 bit)
architecture, which is used in the lowRISC System-on-a-Chip (SoC) Open
Further, lowRISC supports another project to port rump kernels to
minimal RISC-V cores which lowRISC plans to use as I/O co-processors,
for example as TCP/IP offload engines .
There are tool chains and ports of Linux kernels to RISC-V / lowRISC
to run them in simulators and emulators (qemu), on FPGA (Xilinx Zynq),
and ASIC [2, 3].
Although my HW/SW co-design skills are a bit rusty, I am tempted to
reverse that and try such a port. In order to get a better idea about
complexity and effort required, I currently study the sources of
base-hw for ARMv7, and its recent port to x86_64 in the staging
Is anyone aware of such a porting effort, or has anyone else an
interest to run Genode base-hw on RISC-V64, and might want to chime in
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