port samsung exynos 5

Martin Stein martin.stein at ...1...
Thu Jan 22 13:07:59 CET 2015

On 22.01.2015 13:03, Martin Stein wrote:
> My Exynos 5250 manual says that
> uart0_base is 0x12C00000 and uart1_base is 0x12C10000 while uart0/1_clk
> should be the same as uart3_clk but both depend on the configuration
I mean "... same as uart2_clk ..." (the clock Genode uses currently) not

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