interrupts on AMD hardware

[Nobody III]

Thanks for the analysis. The OSDev wiki says, "The ACPICA code is meant to
be directly integrated into the host OS, as a kernel-resident subsystem."
This suggests that we could likely use acpica without too much trouble.

By the way, could you please give me a quick explanation of the _PIC and
_PRT methods, and how they're stored?

On Wed, Apr 4, 2018 at 1:45 AM, Christian Helmuth <
christian.helmuth at ...1...> wrote:

> Hello,
>
> first I'd like to thank Ben for providing me his ACPI tables.
>
> This morning I digged through the disassembled DSDT and got the
> feeling that this AMD platforms depends on an ACPI-capable OS calling
> the _PIC and _PRT methods for IRQ setup. This is the call trace I
> discovered
>
> call _PIC to inform AML of the interrupt model in use
>   _PIC calls \_SB.IRQC in APIC mode
>     \_SB.IRQC configures several SystemIO fields (e.g., PIRA, PIRB)
>
> _PRT reports the routing table as usual referencing AR00 in APIC mode
> so this part should be working already. I suggest further
> investigation of the IRQ-related setup done in the DST AML code.
> Unfortunately, I'm not familiar enough with acpica to know if it could
> be easily adapted to try a full ACPI setup (incl. IRQs) on the
> platform.
>
> Regards
> --
> Christian Helmuth
> Genode Labs
>
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