Writing to UART mapped memory address

[rijurekha at ...71...]

In base-hw/src/core/spec/arm_v7/trustzone/mode_transition.s,
_nonsecure_kernel_entry:, where we go in the monitor handler after a DABT,
we have
mov   r1, #0
mcr   p15, 0, r1, c1, c1, 0 //sets SCR all 0s
cps #SVC_MODE //changes processor mode to SVC

In base-hw/src/core/spec/arm_v7/trustzone/kernel/vm.cc,
in void Vm::exception(unsigned const cpu),
case Genode::Cpu_state::DATA_ABORT:,
Cpu::Scr::read() gives 00000000 and Cpu::Psr::read() gives 600001d3. So
the NS bit in Scr is 0 and the mode bits in CPSR are 10011=19, which is
the SVC mode. So we are getting the correct values that the monitor DABT
handler sets.

We are in the secure SVC mode, when we try to access the  uart physical
address. So what is causing a data abort now?

Thanks!
Riju