Adding Zynq platform support to base-hw

Johannes Schlatow schlatow at ...238...
Fri Dec 19 17:14:49 CET 2014


Hi Martin,

thanks for the hints. I'll check this soon.

I now have a parallella board for testing as well but unfortunately no
breakout board yet to which I could connect a JTAG debugger. Hence I'll
stick to QEMU for the moment.

Cheers and have some nice holidays
 Johannes

On Fri, 19 Dec 2014 16:49:53 +0100
Martin Stein <martin.stein at ...1...> wrote:

> Hi Johannes,
> 
> Sorry for answering that late. I had overlooked your mail.
> 
> Unfortunately the newest qemu version available for my system is 2.0.0
> so there might be differences in our observations. After modifying
> your qemu config from "-m 1024" to "-m 256" I get serial output from
> the beginning of 'init_kernel_up' till
> 'Sctlr::write(Sctlr::init_virt_kernel());' in 'init_kernel_mp ->
> Cpu::init_virt_kernel'. So this seems to be a problem with enabling
> the MMU.
> 
> You could do single-step at this point and check the IP after the
> write to the SCTLR to see in which exception vector you end up (see
> base-hw/src/core/spec/arm_v7/mode_transition.s:
> _mt_kernel_entry_pic). I assume it to be either _dab_entry or
> _pab_entry. If this is the case, reading the ARM registers DFSR/DFAR
> respectively IFSR might help to track down the cause.
> 
> One known problem that arises when enabling the MMU is that this also
> enables ARM caches and branch predictors. You can try deactivating
> them for test purpose.
> 
> 'Z::set(v, 0);' in 'Sctlr::init_virt_kernel' in
> 'base-hw/src/core/include/spec/arm_v7/cpu_support.h' and an empty
> 'Arm_v7::inval_branch_predicts' method should disable branch
> predictors.
> 
> Should 'C::set(v, 0);' and 'I::set(v, 0);' in 'Sctlr::init_common' in
> 'base-hw/src/core/include/spec/arm/cpu_support.h' and adapted TEX/C/B
> fields in the 'CACHED' case in 'Translation::_create' in
> 'base-hw/src/core/include/spec/arm/short_translation_table.h' should
> disable ARM caches.
> 
> You might also check wether your UART and your Core image are mapped
> correctly 1:1 by instrumenting the translation-table methods.
> 
> Cheers,
> Martin
> 
> On 15.12.2014 19:43, Johannes Schlatow wrote:
> > Hey,
> >
> > I just started adding support for the Zynq SoC to base-hw (see [1]).
> >
> > As I don't have any Zynq hardware available yet, I tried running
> > this on QEMU 2.1.2; I compiled the run/hw_info target.
> >
> > After applying some printf debugging ;), I figured out that the
> > program dies (i.e. QEMU freezes) during kernel initialisation
> > in init_virt_kernel(). I therefore tried attaching gdb to QEMU's
> > internal gdb server, however, it seems to ignore my breakpoints.
> >
> > Hence my question: Do you guys have any experience with
> > low-level/kernel debugging on QEMU? Maybe I am missing something or
> > QEMU is just weird?
> >
> > [1]
> > https://github.com/ValiValpas/genode/commit/4e375384d635d06626f0b226ac14e21f608d717a
> >
> > Cheers
> >  Johannes
> >
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> 
> 
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-- 
Johannes Schlatow, M.Sc.

IDA, Institute of Computer and Network Engineering
Technische Universit├Ąt Braunschweig
Hans-Sommer-Str. 66
38106 Braunschweig - Germany

Phone +49 531 391 - 9668

www.ida.ing.tu-bs.de
schlatow at ...238...




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