Writing Pin-muxing registers in an am3359.

[Christian Helmuth]

Hello Bob,

On Thu, Oct 31, 2013 at 07:44:09PM -0400, Bob Stewart wrote:
> I finally got back to looking at this issue and re-read the TI processor 
> document regarding the "Control Module" in the am3359. Apparently the 
> registers in the Control Module can only be written in processor privileged 
> mode and my process would be running in user mode. How can a mechanism be 
> created in Genode to write to such registers?

That's unfortunate. So far, we had not to enable an SoC with the
described behavior. On i.MX31, we side stepped this by reconfiguring
the AHB-to-IP bus interface properly. In my opinion, an appropriate
solution for the issue is a kernel interface for the purpose of
peek/poke on MMIO regions. The interface should be reserved to a
privileged component, i.e. core. Further, the Io_mem service could be
extended by peek/poke RPC methods, which can be invoked by the actual
driver. If the peek/poke service should be subject to a policy
decision, the Io_mem session could be extended by a parameter enabling
the interface.

If you're using base-foc, you may have a look at the
Thread::handle_slow_trap method in the Fiasco.OC sources to add the
kernel interface for peek/poke. In the past, the original Fiasco
kernel (base-fiasco/contrib) provided an interface to execute, e.g.,
wrmsr on x86 with special trap handling. On base-hw, further
extensions to MMIO region handling in the platform-specific part of
core would be needed.

Regards
-- 
Christian Helmuth
Genode Labs

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