Hi Martin,

We have tested the ported code on SABRE Lite board and it is working, except that we need to change UART1 to UART2(0x021e8000).  

Our default console for u-boot is UART2. We tried to see the output of Genode runscript on UART1(by keeping actual values for UART) also but for some reason we see a non-readable output on UART1. This serial port hardware do not have any issues, since we are able to use both the serial ports while running Linux, with same configuration on the same board. If you know of any possible reasons for enabling this to work correctly, please let us know.

Regarding RAM region, is it possible to set default values to 1 GB, as Sabre Lite is having only 1 GB RAM. 
Or 
Is it possible to pass the size(along with the possible UART interface) as an option through a variable in Makefile?
(By this we can keep generic variables and assign these generic values depending on some variable set in make file.)

Apart from these typical configuration changes, we have verified that the image generated from this branch is working successfully on Sabrelite board. 

Regards
Praveen Srinivas
IIT Madras



On Thu, Mar 26, 2015 at 11:00 PM, Praveen B <srinivasprv@...9...> wrote:
Hi Martin,

Good to know the similarities in ESDHC and USDHC. Same method can be adopted for USDHC as the driver does not use CID register(only other 132 bit register).

Taking into consideration all the issues, we have forked another repository, https://github.com/iitmadras/genode and updated the commits. 

Please take a look at it.

On Thu, Mar 26, 2015 at 8:51 PM, Martin Stein <martin.stein@...1...> wrote:
Hi Praveen,

I've created a branch
(https://github.com/m-stein/genode/tree/1467_hw_imx6_support) that works
on our Wandboard Quad and our CuBox-i and opened an according issue
(https://github.com/genodelabs/genode/issues/1467). Some annotations:

* I have not merged the Trustzone support that was started in your
branch as there is no scenario for this right now.

We will update on Trustzone support, once we are confident about it.

* I tried to add the L2-cache support from your branch but it doesn't
work as it is for our boards. Thus, I didn't merge it.

We tried to add L2-cache support. But it is not working for Sabre Lite board as well.  We should have removed it in the previous repository. It is updated in the new repository.

* I modified the kernel to not use the EPIT timer but the CortexA9
Private Timer because it's our default on CortexA9 CPUs and the better
choice when enabling SMP support.

Okay. We will try it on our board. It should work. 

By the way, is SMP enabled for CortexA9 processors in the latest base-hw version? 
Because In our port if we return false for is_smp() function of our board, there is an unresolved page fault in the Core thread. 
We have also assigned variable, NR_OF_CPUS = 1.

* I've merged some redundant code between i.MX6 and i.MX53 into ``spec/imx``

The file 'serial.h' in spec/imx can be an issue for our board, because our board uses UART 0x021e8000 as you mentioned below. We'll think about how to solve it.
 
* I've not merged the uSDHC enums and specs that your i.MX6 port
includes because they should be added by the uSDHC commit

The main differences between our boards and yours seem to be the following:

* the Cortex A9 clock (Wand/Cubox: 792 Mhz, Your board: 800 Mhz) but
this value isn't needed anyway
* the UART instance connected to the serial port (Wand/Cubox:
0x02020000, Your board: 0x021e8000)
* the RAM range configuration

Do you have any objections regarding the commit? If not, I'd suggest you
to re-base your work regarding the i.MX6  onto the branch respectively
the Genode master branch as soon as the commit arrived there to simplify
our collaboration in the future.


We will try to run the code on our board as soon as possible and let you know, If there are any issues.

Regards
Praveen Srinivas
IIT Madras

Cheers,
Martin

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