From 1fd038f508ef2fbde17d68f9b06708362e7863f7 Mon Sep 17 00:00:00 2001
From: Ivan Loskutov <ivan.loskutov@...104...>
Date: Tue, 27 Nov 2012 18:20:23 +0400
Subject: [PATCH 1/2] [base-foc] Enable L2 cache for OMAP4

---
 base-foc/config/panda.kernel                 |    1 +
 base-foc/patches/omap4_l2_cache_enable.patch |  139 ++++++++++++++++++++++++++
 2 files changed, 140 insertions(+), 0 deletions(-)
 create mode 100644 base-foc/patches/omap4_l2_cache_enable.patch

diff --git a/base-foc/config/panda.kernel b/base-foc/config/panda.kernel
index a7e1a59..ed3ff64 100644
--- a/base-foc/config/panda.kernel
+++ b/base-foc/config/panda.kernel
@@ -30,6 +30,7 @@ CONFIG_ARM_CORTEX_A9=y
 # CONFIG_ARM_ALIGNMENT_CHECK is not set
 # CONFIG_ARM_TZ is not set
 CONFIG_ARM_CA9_ENABLE_SWP=y
+CONFIG_ARM_CACHE_L2CXX0=y
 CONFIG_FPU=y
 
 #
diff --git a/base-foc/patches/omap4_l2_cache_enable.patch b/base-foc/patches/omap4_l2_cache_enable.patch
new file mode 100644
index 0000000..1fc3440
--- /dev/null
+++ b/base-foc/patches/omap4_l2_cache_enable.patch
@@ -0,0 +1,139 @@
+diff --git a/kernel/fiasco/src/kern/arm/bsp/omap3/Kconfig b/kernel/fiasco/src/kern/arm/bsp/omap3/Kconfig
+index af74ed8..80e17e6 100644
+--- kernel/fiasco/src/kern/arm/bsp/omap3/Kconfig
++++ kernel/fiasco/src/kern/arm/bsp/omap3/Kconfig
+@@ -31,6 +31,7 @@ config PF_OMAP4_PANDABOARD
+ 	bool "Pandaboard"
+ 	depends on PF_OMAP
+ 	select CAN_ARM_CPU_CORTEX_A9
++	select CAN_ARM_CACHE_L2CXX0
+ 	help
+ 	  Choose for Pandaboard.
+ 
+diff --git a/kernel/fiasco/src/kern/arm/bsp/omap3/Modules b/kernel/fiasco/src/kern/arm/bsp/omap3/Modules
+index e320c7c..a2e4861 100644
+--- kernel/fiasco/src/kern/arm/bsp/omap3/Modules
++++ kernel/fiasco/src/kern/arm/bsp/omap3/Modules
+@@ -23,4 +23,5 @@ timer_tick_IMPL       += timer_tick-single-vector
+ kernel_uart_IMPL      += kernel_uart-arm-omap
+ reset_IMPL            += reset-arm-omap
+ clock_IMPL            += clock-generic
++outer_cache_IMPL      += outer_cache-arm-omap4
+ boot_mp_IMPL          += boot_mp-arm-omap4
+diff --git a/kernel/fiasco/src/kern/arm/bsp/omap3/bootstrap-arm-omap.cpp b/kernel/fiasco/src/kern/arm/bsp/omap3/bootstrap-arm-omap.cpp
+index 403f86e..9b46187 100644
+--- kernel/fiasco/src/kern/arm/bsp/omap3/bootstrap-arm-omap.cpp
++++ kernel/fiasco/src/kern/arm/bsp/omap3/bootstrap-arm-omap.cpp
+@@ -18,4 +18,5 @@ map_hw(void *pd)
+   map_1mb(pd, Mem_layout::Devices2_map_base, Mem_layout::Devices2_phys_base, false, false);
+   map_1mb(pd, Mem_layout::Devices3_map_base, Mem_layout::Devices3_phys_base, false, false);
+   map_1mb(pd, Mem_layout::Devices4_map_base, Mem_layout::Devices4_phys_base, false, false);
++  map_1mb(pd, Mem_layout::Devices5_map_base, Mem_layout::Devices5_phys_base, false, false);
+ }
+diff --git a/kernel/fiasco/src/kern/arm/bsp/omap3/mem_layout-arm-omap.cpp b/kernel/fiasco/src/kern/arm/bsp/omap3/mem_layout-arm-omap.cpp
+index 202fc5f..c18fb93 100644
+--- kernel/fiasco/src/kern/arm/bsp/omap3/mem_layout-arm-omap.cpp
++++ kernel/fiasco/src/kern/arm/bsp/omap3/mem_layout-arm-omap.cpp
+@@ -93,6 +93,7 @@ public:
+     Devices2_phys_base       = 0x48200000,
+     Devices3_phys_base       = 0x4a300000,
+     Devices4_phys_base       = 0x49000000,
++    Devices5_phys_base       = 0x4a000000,
+     Sdram_phys_base          = 0x80000000,
+   };
+ 
+@@ -101,9 +102,11 @@ public:
+     Devices2_map_base       = Registers_map_start + 0x00100000,
+     Devices3_map_base       = Registers_map_start + 0x00200000,
+     Devices4_map_base       = Registers_map_start + 0x00300000,
++    Devices5_map_base       = Registers_map_start + 0x00400000,
+ 
+     Uart_base               = Devices1_map_base + 0x20000,
+     Mp_scu_map_base         = Devices2_map_base + 0x40000,
++    L2cxx0_map_base         = Devices2_map_base + 0x42000,
+     Gic_cpu_map_base        = Devices2_map_base + 0x40100,
+     Gic_dist_map_base       = Devices2_map_base + 0x41000,
+ 
+@@ -111,5 +114,7 @@ public:
+     __PL310 = Devices2_map_base + 0x42000,
+ 
+     Prm_map_base            = Devices3_map_base + 0x6000,
++
++    Scm_map_base            = Devices5_map_base + 0x2000,
+   };
+ };
+diff --git a/kernel/fiasco/src/kern/arm/bsp/omap3/outer_cache-arm-omap4.cpp b/kernel/fiasco/src/kern/arm/bsp/omap3/outer_cache-arm-omap4.cpp
+new file mode 100644
+index 0000000..c924bb6
+--- /dev/null
++++ kernel/fiasco/src/kern/arm/bsp/omap3/outer_cache-arm-omap4.cpp
+@@ -0,0 +1,57 @@
++IMPLEMENTATION [arm && omap4 && outer_cache_l2cxx0]:
++
++
++PRIVATE INLINE static
++void
++Outer_cache::smc1(Mword arg0, Mword arg1)
++{
++  register unsigned long r0  asm("r0")  = arg1;
++  register unsigned long r12 asm("r12")  = arg0;
++
++  asm volatile("dsb; smc #0"
++               : : "r" (r0), "r" (r12)
++               : "r2", "r3", "r4", "r5", "r6",
++                 "r7", "r8", "r9", "r10", "r11", "lr", "memory");
++}
++
++IMPLEMENT
++Mword
++Outer_cache::platform_init(Mword aux_control)
++{
++  // check revision
++  Mword idcode = Io::read<Mword>(Mem_layout::Scm_map_base + 0x0204);
++  unsigned hawkeye = (idcode >> 12) & 0xffff;
++  unsigned rev = (idcode >> 28) & 0xf;
++
++  // check omap4430_rev_es1_0
++  bool is_rev_es_1_0 = (hawkeye == 0xb852) && (rev == 0);
++
++  Mword aux_ctrl = ((1 << 16) |         // L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT
++                     (0x1 << 25) |
++                     (0x1 << 26) |      // L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT
++                     (0x1 << 27));      // L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT
++
++  /*
++   * 16-way associativity, parity disabled
++   * Way size - 32KB (es1.0)
++   * Way size - 64KB (es2.0 +)
++   */
++  if (is_rev_es_1_0)
++      aux_ctrl |= 0x2 << 17;            // L2X0_AUX_CTRL_WAY_SIZE_SHIFT
++  else
++      aux_ctrl |= ((0x3 << 17) |        // L2X0_AUX_CTRL_WAY_SIZE_SHIFT
++             (0x1 << 22) |              // L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT
++             (0x1 << 28) |              // L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT
++             (0x1 << 29) |              // L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT
++             (0x1 << 30));              // L2X0_AUX_CTRL_EARLY_BRESP_SHIFT
++
++  if (!is_rev_es_1_0)
++    Outer_cache::smc1(0x109, aux_ctrl);
++
++  Outer_cache::smc1(0x102, 0x1);
++  
++  aux_control &= 0xc0000fff;
++  aux_control |= aux_ctrl;
++
++  return aux_control;
++}
+diff --git a/kernel/fiasco/src/templates/globalconfig.out.arm-omap4-panda b/kernel/fiasco/src/templates/globalconfig.out.arm-omap4-panda
+index 24de395..2b83b1b 100644
+--- kernel/fiasco/src/templates/globalconfig.out.arm-omap4-panda
++++ kernel/fiasco/src/templates/globalconfig.out.arm-omap4-panda
+@@ -26,6 +26,7 @@ CONFIG_PF_ARM_MP_CAPABLE=y
+ CONFIG_CAN_ARM_CPU_CORTEX_A9=y
+ CONFIG_ARM_CORTEX_A9=y
+ CONFIG_ARM_ALIGNMENT_CHECK=y
++CONFIG_ARM_CACHE_L2CXX0=y
+ # CONFIG_ARM_TZ is not set
+ CONFIG_ARM_CA9_ENABLE_SWP=y
+ CONFIG_FPU=y
-- 
1.7.8.6

